Fin-type transistors have been widely employed in, for example, sub-22 nm technology due to its ability to provide better performance, such as higher drive current, improved short channel effect and lower off-state leakages. Fin-type transistors are also preferred based on its ability for higher packing density. Forming fin-type field effect transistor (FinFET) on bulk substrates with junction isolation is generally used as a lower manufacturing cost solution relative to forming one on silicon on insulator (SOI) substrates. However, as devices continue to shrink, the source to drain leakage increases exponentially. To mitigate this, more channel/well doping is required, which leads to undesirable mobility/performance degradation. This further impedes scaling and may lead to the use of SOI FinFET to reduce leakages. The existing SOI FinFET solution, however, is relatively expensive and no body bias is possible. Additionally, self-heating effect which may result in performance degradation is commonly observed in such SOI devices.
From the foregoing discussion, it is desirable to provide fin type devices which are devoid of the above-mentioned problems and with improved performance. It is also desirable to provide efficient and cost effective methods for forming such devices.